To achieve efficient data transfer by minimizing the number of times of the data transfer, a conventional data transfer device based on a DMA method sets the maximum transfer unit allowed from a plurality of predetermined transfer units according to a data volume to be transferred, and transfers the data at the transfer unit, followed by repeating, in accordance with the remaining data volume, the processing of setting the maximum transfer unit allowed and of transferring the data at the transfer unit until the data to be transferred is reduced to zero (see Patent Document 1, for example).
Patent Document 1: Japanese Patent Laid-Open No. 2000-187636.
With the foregoing configuration, the conventional data transfer device aims at only transferring data efficiently by minimizing the number of times of the transfer, but does not consider the number of times of the setting processing of the transfer unit. In addition, as for the transfer unit settings, since a CPU (Central Processing Unit) performs them, a greater number of times of the transfer unit settings at the data transfer offers a problem of increasing the load of the CPU by that amount.
The present invention is implemented to solve the foregoing problem. Therefore it is an object of the present invention to provide a data transfer device and data transfer method capable of reducing the load of the CPU at the data transfer by limiting the number of times of the transfer unit settings.